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XMEGA A [MANUAL]
8077I–AVR–11/2012
11.7
Registers Description
11.7.1 CTRL – Control register
Bits 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero
when this register is written.
Bits 5:2 – PER[3:0]: Timeout Period
These bits determine the watchdog timeout period as a number of 1kHz ULP oscillator cycles. In window mode
operation, these bits define the open window period. The different typical timeout periods are found in
Table 11-1. The
initial values of these bits are set by the watchdog timeout period (WDP) fuses, which are loaded at power-on.
In order to change these bits, the CEN bit must be written to 1 at the same time. These bits are protected by the
Table 11-1.
Watchdog timeout periods.
Note:
Reserved settings will not give any timeout.
Bit
7
65
43
210
+0x00
–
PER[3:0]
ENABLE
CEN
Read/Write (unlocked)
R
R/W
Read/Write (locked)
R
Initial Value (x = fuse)
0
X
0
PER[3:0]
Group configuration
Typical timeout periods
0000
8CLK
8ms
0001
16CLK
16ms
0010
32CLK
32ms
0011
64CLK
64ms
0100
128CLK
0.128s
0101
256CLK
0.256s
0110
512CLK
0.512s
0111
1KCLK
1.0s
1000
2KCLK
2.0s
1001
4KCLK
4.0s
1010
8KCLK
8.0s
1011
Reserved
1100
Reserved
1101
Reserved
1110
Reserved
1111
Reserved